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6. Read Operations
Read operations are initiated the same way as write operations with the exception that the
Read/Write select bit in the device address word is set to “1”. There are three read operations:
current address read, random address read and sequential read.
CURRENT ADDRESS READ: The internal data word address counter maintains the last
address accessed during the last read or write operation, incremented by “1”. This address stays
valid between operations as long as the chip power is maintained. The address roll over during
read is from the last byte of the last memory page, to the first byte of the first page.
Once the device address with the Read/Write select bit set to “1” is clocked in and acknowl-
edged by the EEPROM, the current address data word is serially clocked out. The
microcontroller does not respond with an input “0” but does generate a following stop condition
(see Figure 6-4 on page 11 ).
RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data
word address. Once the device address word and data word address are clocked in and
acknowledged by the EEPROM, the microcontroller must generate another start condition. The
microcontroller now initiates a current address read by sending a device address with the
Read/Write select bit high. The EEPROM acknowledges the device address and serially clocks
out the data word. The microcontroller does not respond with a “0” but does generate a following
stop condition (see Figure 6-5 on page 11 ).
SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a ran-
dom address read. After the microcontroller receives a data word, it responds with an
acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment
the data word address and serially clock out sequential data words. When the memory address
limit is reached, the data word address will roll over and the sequential read will continue. The
sequential read operation is terminated when the microcontroller does not respond with a “0” but
does generate a following stop condition (see Figure 6-6 on page 11 ).
Figure 6-1.
Device Address
1
0
1
0
A 2
A 1
A 0
R/W
MSB
LSB
Figure 6-2.
Byte Write
10
AT24C512B
5297A–SEEPR–1/08
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